As shown in FIG. 1, the twin-transistor Electrically Erasable Programmable Read-only Memory is composed of a storage array and a peripheral circuit. The peripheral circuit includes such circuits as a pre decoder, a row decoder, a column decoder, a high voltage selector, a logic controller (Control logic), a word line driver of the grid of the storage cell (SWL driver), a column selector, and a sense amplifier.
The sense amplifier circuit is used for distinguishing between ‘0’ Storage Cell and ‘1’ Storage Cell safely and reliably with a storage cell current and the reference current of the non-volatile memory under various process conditions, ranges of the power supply voltage and temperature conditions. A traditional sense amplifier circuit as shown in FIG. 2 is designed in such a way that a reference storage cell or a resistor is used to generate the reference current, which compensates the process conditions and the temperature characteristics to some extent, however generally does not compensate influence of the power supply voltage. The main circuit includes a load compensation circuit 1, a first-stage amplifying circuit 2, a second-stage amplifying circuit 3, and a sequence generation circuit 4. Such a circuit is more effective under the condition that characteristics of the storage cell do not change much with the process, however gradually shows its limitation with the characteristic size reduced continuously; in addition, such a design cannot usually attain the requirements on an occasion where very high reliability is required.